At dawn of the computer era digital computers were made of blocks performing elementary logic functions. The majority of these building blocks were operating at the same clock frequency. Increase in computer performance was achieved by clock frequency increase and development of specialized/dedicated building blocks like memory chips, CPU (Central Processing Unit) chips, I/O (Input/Output) chips etc. Uneven progress in development of different types of chips and/or computer architectural demands resulted in development of computers comprising different chips operating at different clock frequencies. Further development along this trajectory resulted in different clock domains within one chip or even on one die. In return a new problem emerged, i.e. implementation of low latency data transfer between these clock domains. This problem gets further complicated when data has to be transferred between clock domains having a variable clock frequency. For instance, it is a common practice when a CPU clock domain having a variable clock frequency communicates with other devices via an I/O clock domain having a fixed clock frequency. As usual various buffers are used as intermediate storage elements for a data transfer between the clock domains. A state of the art approach is based on utilization of one buffer per data channel connecting the clock domains.